


module bus_isr(
    input clk , 
    input rst_n , 

    input  wire [7:0]  m_dat_i  , 
    output wire [7:0]  m_dat_o  , 
    input  wire [7:0]  m_adr_i , 
    input  wire        m_wen_i  ,

    // 
    input wire [7:0]   isr_req_i ,
    output reg [7:0]   interrupt_o 
) ;

reg [7:0] isr_flag ; 
reg [7:0] isr_req_d1 ;
reg [7:0] isr_req_d2 ;

always @(posedge clk ) begin
    if(rst_n==1'b0) begin
        isr_req_d1 <= 8'h0 ;
        isr_req_d2 <= 8'h0 ;
    end else begin
        isr_req_d1 <= isr_req_i ;
        isr_req_d2 <= isr_req_d1 ;
    end
end

always @(posedge clk ) begin
    if(~rst_n) begin
        isr_flag <= 8'h0 ;
        interrupt_o <= 1'b0 ;
    end else begin
        interrupt_o <= 1'b0 ;
        if(m_wen_i) begin
            case(m_adr_i)
                8'h00: begin 
                    isr_flag <= 8'h00 ;
                    $display(" -------------- clear interrupt --------------" ) ;
                end 
            endcase  
        end 


        if(~isr_req_d2 & isr_req_d1) begin
            isr_flag <= ((m_wen_i & ~|m_adr_i)? 8'h00 : isr_flag) | ( ~isr_req_d2 & isr_req_d1) ;
            interrupt_o <= 1'b1 ;
            $display("%t ns | isr=0x%02x" , $time , isr_flag | ( ~isr_req_d2 & isr_req_d1)) ;
        end

    end
end

assign m_dat_o = isr_flag ;

endmodule 

